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18Mb Pipelined QDRTMII SRAM Burst of 4
Features
x x x x x x
Description
Advance Information IDT71P74204 IDT71P74104 IDT71P74804 IDT71P74604
x x x
x x x
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36) Separate, Independent Read and Write Data Ports Supports concurrent transactions Dual Echo Clock Output 4-Word Burst on all SRAM accesses Multiplexed Address Bus One Read or One Write request per clock cycle DDR (Double Data Rate) Data Bus Four word burst data per two clock cycles on each port Four word transfers per clock cycle Depth expansion through Control Logic HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V to 1.9V. Scalable output drivers Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. Output Impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage (VDD) 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package JTAG Interface
The IDT QDRIITM Burst of four SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read and write data ports. This scheme allows simultaneous read and write access for the maximum device throughput, with four data items passed with each read or write. Four data word transfers occur per clock cycle, providing quad-data-rate (QDR) performance. Comparing this with standard SRAM common I/O (CIO), single data rate (SDR) devices, a four to one increase in data access is achieved at equivalent clock speeds. Considering that QDRII allows clock speeds in excess of standard SRAM devices, the throughput can be increased well beyond four to one in most applications. Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds. The QDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. The QDRII has a single SDR address bus with read addresses and write addresses multiplexed. The read and write addresses interleave with each occurring a maximum of every other cycle. In the event that no operation takes place on a cycle, the subsequest cycle may begin with either a read or write. During write operations, the writing of individual bytes may be blocked through the use of byte or nibble write control signals. The QDRII has echo clocks, which provide the user with a clock
Functional Block Diagram
D
(Note1)
DATA REG WRITE DRIVER
SENSE AMPS
OUTPUT REG
SA
OUTPUT SELECT
OUTPUT SELECT
(Note2)
ADD REG
WRITE/READ DECODE
(Note2)
R W BWx
(Note3)
CTRL LOGIC
18M MEMORY ARRAY
(Note1)
Q
K K C C
CLK GEN SELECT OUTPUT CONTROL
CQ CQ
6111 drw16 Notes 1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36 2) Represents 19 address signal lines for x8 and x9, 18 address signal lines for x18, and 17 address signal lines for x36. 3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a "nibble write" and there are 2 signal lines.
MARCH 2004
1
(c)2003 Integrated Device Technology, Inc. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. " DSC-6111/00
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
that is precisely timed to the data output, and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source. All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. The device is capable of sustaining full bandwidth on both the input and output ports simultaneously. All data is in two word bursts, with addressing capability to the burst level.
edge of CQ, and the falling edge of CQ. The rising edge of C generates the rising edge of CQ and the falling edge of CQ. This scheme improves the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. The echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated.
Read and Write Operations
QDRII devices internally store the 4 words of the burst as a single, wide word and will retain their order in the burst. There is no ability to address to the single word level or reverse the burst order; however, the byte and nibble write signals can be used to prevent writing any individual bytes, or combined to prevent writing one word of the burst. Read and write operations may be interleaved with each occurring on every other clock cycle. In the event that two reads or two writes are requested on adjacent clock cycles, the operation in progress will complete and the second request will be ignored. In the event that both a read and write are requested simultaneously, the read operation will win and the write operation will be ignored. Read operations are initiated by holding the read port select (R) low, and presenting the read address to the address port during the rising edge of K which will latch the address. The data will then be read and will appear at the device output at the designated time in correspondence with the C and C clocks. Write operations are initiated by holding the write port select (W) low and presenting the designated write address to the address bus. The QDRII SRAM will receive the address on the rising edge of clock K. On the following rising edge of K clock, the QDRII SRAM will receive the first data item of the four word burst on the data bus. Along with the data, the byte (BW) or nibble write (NW) inputs will be accepted, indicating which bytes of the data inputs should be written to the SRAM. On the rising edge of K, the next word of the write burst and BW/NW will be accepted. The following K and K will receive the last two words of the four word burst, with their BW/NW enables.
Clocking
The QDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the QDRII has an output "echo" clock, CQ, CQ. The K and K clocks are the primary device input clocks. The K clock is, used to clock in the control signals (R, W and BWx/NWx), the address, first and third words of the data burst during a write operation. The K clock is used to clock in the control signals (BWx or NWx) and the second and fourth words of the data burst during a write operation. The K and K clocks are also used internally by the SRAM. In the event that the user disables the C and C clocks, the K and K clocks will be used to clock the data out of the output register and generate the echo clocks. The C and C clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. C and C must be presented to the SRAM within the timing tolerances. The output data from the QDRII will be closely aligned to the C and C input, through the use of an internal DLL. When C is presented to the QDRII SRAM, the DLL will have already internally clocked the data to arrive at the device output simultaneously with the arrival of the C clock. The C and second data item of the burst will also correspond. The third and fourth data items will follow on the next clock cycle.
Output Enables
The QDRII SRAM automatically enables and disables the Q[X:0] outputs. When a valid read is in progress, and data is present at the output, the output will be enabled. If no valid data is present at the output (read not active), the output will be disabled (high impedance). The echo clocks will remain valid at all times and cannot be disabled or turned off. During power-up the Q outputs will come up in a high impedance state.
Single Clock Mode
The QDRII SRAM may be operated with a single clock pair. C and C may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the K and K clocks.
DLL Operation
The DLL in the output structure of the QDRII SRAM can be used to closely align the incoming clocks C and C with the output of the data, generating very tight tolerances between the two. The user may disable the DLL by holding Doff low. With the DLL off, the C and C (or K and K if C and C are not used) will directly clock the output register of the SRAM. With the DLL off, there will be a propagation delay from the time the clock enters the device until the data appears at the output.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output drive impedance. The value of RQ must be 5X the value of the intended drive impedance of the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of +/- 10% is between 175 ohms and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the SRAM to it's lowest value, the ZQ pin may be tied to VDDQ.
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C clocks (or K, K if C, C are disabled). The rising edge of C generates the rising
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Pin Definitions
Symbol Pin Function Description Data input signals, sampled on the rising edge of K and K clocks during valid write operations 2M x 8 -- D[7:0] 2M x 9 -- D[8:0] 1M x 18 -- D[17:0] 512K x 36 -- D[35:0] Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations . Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device. 2M x 9 -- BW0 controls D[8:0] 1M x 18 -- BW0 controls D[8:0] and BW1 controls D[17:9] 512K x 36 -- BW0 controls D[8:0], BW1 controls D[17:9], BW2 controls D[26:18] and BW3 controls D[35:27] Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the rising edge of the K and K clocks during write op erations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles no t written remain unaltered. All the nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written in to the device. Address inputs are sampled on the rising edge of K clock during active read or write operations. These address inputs are multiplexed so a read and write can be initiated on alternate clock cycles. These inputs are ignored when the appropriate port is deselected.
D[X:0]
Input Synchronous
BW0, BW1 BW2, BW3
Input Synchronous
NW0, NW1
Input Synchronous
SA
Input Synchronous
Q[X:0]
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising Output Synchronous edge of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the Read port is deselected, Q[X:0] are automatically three-stated. Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation in initiated. Deasserting will deselect the Write port, causing D[X:0] to be ignored. If a write operation has successfully been initiated, it will continue to completion, ignoring the W on the following clock cycle. This allows the user to continuously hold W low while bursting data into the SRAM. Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of four sequential transfer. If a read operation has successfully been initiate d, it will continue to completion, ignoring the R on the following clock cycle. This allows the user to continuously hold R low while bursting data from the SRAM. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[X:0] when in single cloc k mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[X:0] when in single clock mode. Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals are free running and do not stop when the output data is threestated. Output Impedance Matching Input. This input is us ed to tune the device outputs to the sys tem data bus impedance. Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
6111 tbl 02a
W
Input Synchronous
R
Input Synchronous
C
Input Clock
C
Input Clock
K
Input Clock
K
Input Clock
CQ, CQ
Output Clock
ZQ
Input
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Pin Definitions continued
Symbol Pin Function Description DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet. There will be an increased propagation delay from the incidence of C and C to Q, or K and K to Q as configured. The propagation delay is not a tested parameter, but will be similar to the propagation delay of other SRAM devic es in this speed grade. TDO pin for JTAG. TCK pin for JTAG. TDI pin for JTAG. An internal resistor will pull TDI to VDD when the pin is unconnected. TMS pin for JTAG. An internal resistor will pull TMS to VDD when the pin is unconnected. No connects inside the package. Can be tied to any voltage level Reference Voltage input. Static input used to set the reference le vel for HSTL inputs and Outputs as well as AC measurement points. Power supply inputs to the co re of the device. Should be connected to a 1.8V power supply. Ground for the device. Should be connected to ground of the system. Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.
6111 tbl 02b
Doff
Input
TDO TCK TDI TMS NC
Output Input Input Input No Connect Input Reference Power Supply Ground Power Supply
VREF
VDD
VSS
VDDQ
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Pin Configuration 2M x 8
1 A B C D E F G H J K L M N P R
2 VSS/ SA (2) NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK
3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA
4
5
6
7 NC
8
9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA
10 VSS/ SA (1) NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS
6111 tbl 12
11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
CQ
NC NC NC NC NC NC
W
SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
NW1
NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
K
K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C
R
SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
NW0
SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
Doff
NC NC NC NC NC NC TDO
C
165-ball FBGA Pinout TOP VIEW
NOTES: 1. A10 is reserved for the 36Mb expansion address. 2. A2 is reserved for the 72Mb expansion address.
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Pin Configuration 2M x 9
1 A B C D E F G H J K L M N P R
2 VSS/ SA (2) NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK
3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA
4
5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
6
7 NC
8
9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA
10 VSS/ SA (1) NC NC NC D2 NC NC VREF Q1 NC NC NC NC D8 TMS
11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC Q8 TDI
CQ
NC NC NC NC NC NC
W
SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
K
K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C
R
SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
BW
SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
Doff
NC NC NC NC NC NC TDO
C
6111 tbl 12a
165-ball FBGA Pinout TOP VIEW
NOTES: 1. A10 is reserved for the 36Mb expansion address. 2. A2 is reserved for the 72Mb expansion address.
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Pin Configuration 1M x 18
1 A B C D E F G H J K L M N P R 2 VSS/ SA (3) Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC/ SA (1) D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 5 6 7 NC 8 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 VSS/ SA (2) NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
CQ
NC NC NC NC NC NC
W
SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
BW1
NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
K
K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C
R
SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
BW0
SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
Doff
NC NC NC NC NC NC TDO
C
6111 tbl 12b
165-ball FBGA Pinout TOP VIEW
NOTES: 1. A3 is reserved for the 36Mb expansion address. 2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices. 3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Pin Configuration 512K x 36
1 A B C D E F G H J K L M N P R 2 VSS/ SA (4) Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 NC/ SA (2) D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 SA 4 5 6 7 8 9 NC/ SA (1) D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA 10 VSS SA (3) Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS
6111 tb l 12c
11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
CQ
Q27 D27 D28 Q29 Q30 D30
W
SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
BW2 BW3
SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
K
K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C
BW1 BW0
SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
R
SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
Doff
D31 Q32 Q33 D33 D34 Q35 TDO
C
165-ball FBGA Pinout TOP VIEW
NOTES: 1. A9 is reserved for the 36Mb expansion address. 2. A3 is reserved for the 72Mb expansion address. 3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices. 4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Absolute Maximum Ratings(1) (2)
Symbol VTERM VTERM VTERM VTERM TBIAS TSTG IOUT Rating Supply Voltage on VDD with Respect to GND Supply Voltage on VDDQ with Respect to GND Voltage on Input terminals with respect to GND Voltage on Output and I/O terminals with respect to GND. Temperature Under Bias Storage Temperature Continuous Current into Outputs Value -0.5 to +2.9 -0.5 to VDD +0.3 -0.5 to VDD +0.3 -0.5 to VDDQ +0.3 -55 to +125 -65 to +150 + 20 Unit V V V V C C mA
Capacitance (TA = +25C, f = 1.0MHz)(1)
Symbol CIN CCLK CO Parameter Input Capacitance Clock Input Capacitance Output Capacitance VDD = 1.8V VDDQ = 1.5V Conditions Max. 5 6 7 Unit pF pF pF
6111 tbl 06
NOTE: 1. Tested at characterization and retested after any design or process change that may affect these parameters.
NOTES: 6111 tbl 05 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation.
Recommended DC Operating and Temperture Conditions
Symbol VDD VDDQ VSS VREF TA Parameter Power Supply Voltage I/O Supply Voltage Ground Input Reference Voltage Ambient Temperature
(1)
Min. 1.7 1.4 0 0.68 0
Typ. 1.8 1.5 0 VDDQ/2 25
Max. 1.9 1.9 0 0.95 +70
Unit V V V V
o
c
Write Descriptions (1,2)
Signal Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Write Nibble 0 Write Nibble 1
NOTE: 1. During production testing, the case temperarure equals the ambient temperature.
6111 tbl 04
BW0
L X X X X X
BW1
X L X X X X
BW2
X X L X X X
BW3
X X X L X X
NW0
X X X X L X
NW1
X X X X X L
6111 tbl 09
NOTES: 1) All byte write (BWx) and nibble write (NWx) signals are sampled on the rising edge of K and again on K. The data that is present on the data bus in the designated byte/nibble will be latched into the input if the corresponding BWx or NWx is held low. The rising edge of K will sample the first and third bytes/ nibbles of the four word burst and the rising edge of K will sample the second and fourth bytes/nibbles of the four word burst. 2) The availability of the BWx or NWx on designated devices is described in the pin description table. 3) The QDRII Burst of four SRAM has data forwarding. A read request that is initiated on the cycle following a write request to the same address will produce the newly written data in response to the read request.
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Application Example
W
SRAM #1 D SA R W B W 0 B W 1 C C ZQ Q KK 250
SRAM #4
VT R Data In Data Out Address R W BWx/NWx MEMORY CONTROLLER Return CLK Source CLK Return CLK Source CLK R = 50
D SA R W BW0 BW1 CC
ZQ Q KK
R R R R R
250
VT
VT VT R R
VT = VREF
6111 drw 20
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V)
Param eter Inp ut Le akag e Curre nt Outp ut Le akag e Curre nt Sym bol IIL IOL Test Conditions VDD = M ax VIN = VSS to VDDQ Outp ut Disab le d 333M HZ Op e rating Curre nt (x36,x18,x 9,x 8): DDR VDD = M ax , IO UT = 0m A (o utp uts o p e n), Cyc le Tim e > tKHKH M in 300M HZ 250M HZ 300M Hz 167M Hz 333M HZ De vice De s e le cte d (in NOP state ) IO UT = 0m A (o utp uts o p e n), f=M ax, All Inp uts <0.2V o r > V DD -0.2V 300M HZ 250M HZ 200M Hz 167M Hz Outp ut Hig h Vo ltag e Outp ut Lo w Vo ltag e Outp ut Hig h Vo ltag e Outp ut Lo w Vo ltag e VO H1 VOL1 VO H2 VOL2 RQ = 250, IOH = -15m A RQ = 250, IOL = 15mA IOH = -0.1m A IOL = 0.1m A Min -10 -10 VDDQ/2-0.12 VDDQ/2-0.12 VDDQ -0.2 VSS Max +10 +10 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD VDDQ /2+0.12 VDDQ /2+0.12 VDDQ 0.2 V V V V 3,7 4,7 5 6
6111 tb l 10 c
Unit A A
Note
IDD
mA
1
Stand b y Curre nt: NOP
IS B1
mA
2
NOTES: 1. Operating Current is measured at 100% bus utilization. 2. Standby Current is only after all pending read and write burst operations are completed. 3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175 < RQ < 350. This parameter is tested at RQ = 250, which gives a nominal 50 output impedance. 4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175 < RQ < 350. This parameter is tested at RQ = 250, which gives a nominal 50 output impedance. 5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an impedance measurement point. 6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance measurement point. 7. Programmable Impedance Mode.
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V)
PARAMETER Input High Voltage, DC Input Low Voltage, DC Input High Voltage, AC Input Low Voltage, AC SYMBOL VIH (DC) VIL (DC) VIH (AC) VIL (AC) MIN VREF +0.1 -0.3 VREF +0.2 MAX VDDQ +0.3 VREF -0.1 VREF -0.2 UNIT V V V V NOTES 1,2 1,3 4,5 4,5
6111 tbl 10d NOTES: 1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min)) 3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min)) 4. This conditon is for AC function test only, not for AC parameter test. 5. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC) b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Overshoot Timing
20% tKHKH (MIN) VDD +0.5 VDD +0.25 VDD
Undershoot Timing
VIH
VSS VSS-0.25V
VIL
6111 drw 21
VSS-0.5V
6111 drw 22
20% tKHKH (MIN)
AC Test Load
AC Test Conditions
Parameter Core Power Supply Voltage Symbol VDD VDDQ VIH/VIL VREF TR/TF Value 1.7-1.9 1.4-1.9 1.25/0.25 0.75 0.6/0.6 VDDQ/2 Unit V V V V ns V
6111tbl 11a
VREF OUTPUT Device Under Test ZQ
0.75V
Output Power Supply Voltage Input High/Low Level Input Reference Level
Z0 =50 RQ = 250
RL = 50 VDDQ /2
Input Rise/Fall Time Output Timing Reference Level
NOTE: 1. Parameters are tested with RQ=250
6111 drw 04
1.25V 0.75V 0.25V
6111 drw 06
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
AC Electrical Characteristics
Symbol Clock Parameters tKHKH tKC var tKHKL tKLKH tKHKH tKHKH tKHCH tKC lock tKC reset Average clock cycle time (K,K,C,C) Cycle to Cycle Period Jitter (K,K,C,C) Clock High Time (K,K,C,C) Clock LOW Time (K,K,C,C) Clock to clock (KK,CC) Parameter
(VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V,TA = 0 TO 70C)(3,8)
333MHz 300MHz Min. Max 250MHz Min. Max 200MHz Min. Max 167MHz Min. Max Unit Notes Max
Min.
3.00 1.20 1.20 1.35 1.35 0.00 1024 30
3.47 0.20 1.30 -
3.30 1.32 1.32 1.49 1.49 0.00 1024 30
5.25 0.20 1.45 -
4.00 1.60 1.60 1.80 1.80 0.00 1024 30
6.30 0.20 1.80 -
5.00 2.00 2.00 2.20 2.20 0.00 1024 30
7.88 0.20 2.30 -
6.00 2.40 2.40 2.70 2.70 0.00 1024 30
8.40 0.20 2.80 -
ns ns ns ns ns ns ns cycles ns 2 1,5 9 9 10 10
Clock to clock (KK,CC)
Clock to data clock (KC,KC) DLL lock time (K, C) K static to DLL reset
Output Parameters tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ tCHQX1 C,C HIGH to output valid C,C HIGH to output hold C,C HIGH to echo clock valid C,C HIGH to echo clock hold CQ,CQ HIGH to output valid CQ,CQ HIGH to output hold C HIGH to output High-Z C HIGH to output Low-Z -0.45 -0.45 -0.25 -0.45 0.45 0.45 0.25 0.45 -0.45 -0.45 -0.27 -0.45 0.45 0.45 0.27 0.45 -0.45 -0.45 -0.30 -0.45 0.45 0.45 0.30 0.45 -0.45 -0.45 -0.35 -0.45 0.45 0.45 0.35 0.45 -0.50 -0.50 -0.40 -0.50 0.50 0.50 0.40 0.50 ns ns ns ns ns ns ns ns 3,4,5 3,4,5 3 3 3 3
Set-Up Times tAVKH tIVKH tDVKH Address valid to K,K rising edge Control inputs valid to K,K rising edge Date-in valid to K, K rising edge 0.40 0.40 0.30 0.40 0.40 0.30 0.50 0.50 0.35 0.60 0.60 0.40 0.70 0.70 0.50 ns ns ns 6 7
Hold Times tKHAX tKHIX tKHDX K,K rising edge to address hold K,K rising edge to control inputs hold K, K rising edge to data-in hold 0.40 0.40 0.30 0.40 0.40 0.30 0.50 0.50 0.35 0.60 0.60 0.40 0.70 0.70 0.50 ns ns ns
6111 tbl 11
6 7
NOTES: 1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65 (EIA/JESD65) pg.10 2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. 3. If C,C are tied High, K,K become the references for C,C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. 5. This parameter is guaranteed by device characterization, but not production tested. 6. All address inputs must meet the specified setup and hold times for all latching clock edges. 7. Control signals are R, W,BW0,BW1 and (NW0,NW1, for x8) and (BW2,BW3 also for x36) 8. During production testing, the case temperature equals TA. 9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH). 10. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Timing Waveform of Combined Read and Write Cycles
NOP 1 Read A0 2 Write A1 3 Read A2 4 Write A3 5 NOP 6 NOP 7
K
tKHKL tKLKH tKHKH tKHKH
K
R
tIVKH tKHIX tIVKH tKHIX
W
SA
A0
A1
tKHDX
A2
A3
tKHDX tDVKH
tAVKH tKHAX
tDVKH
D
D10
D11
D12
D13
D30
D31
D32
D33
Q
Qx2
Qx3
Q00
Q01
Q02
Q03
Q20
Q21
Q22
Q23
tCHQV tKHCH tCHQX1 tCHQV tCHQX
tCHQX tCQHQV
tCHQZ tCQHQX
C
tKHKH tKHCH tKHKH
.
tKHKL
tKLKH
C
tCHCQV tCHCQX
CQ
tCHCQV tCHCQX
CQ
6111 drw09
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may also be tied to VDD through a register. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 0 0 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE SAMPLE-Z RESERVED TDO Output Boundary Scan Register Identification register Boundary Scan Register Do Not Use 2 1 5 4 5 5 3
6111tbl 13
Notes
SA,D K,K C,C Q CQ CQ
0
SRAM CO RE
0 1 1 1
SAMPLE/PRELOAD Boundary Scan register RESERVED RESERVED BYPASS Do Not Use Do Not Use Bypass Register
TDI
BYPASS R eg. Iden tification R eg . Ins truc tion Reg . Control Signa ls
TDO
1
NOTES:
TMS TCK
T AP Co ntro lle r
6111 drw 18
TAP Controller State Diagram
1 Test Logic Reset 0 Run Test Idle 1 Select DR 0 1 Capture DR 0 Shift DR 1 1 Exit 1 DR 0 Pause DR 1 Exit 2 DR 1 1 Update DR 0 0 1 1 1 Select IR 0 Capture IR 0 Shift IR 1 Exit 1 IR 0 Pause IR 1 Exit 2 IR 1 Update IR 1 0 1
1. Places Qs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initialized to Vss when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when existing the Shift DR states. 4. SAMPLE instruction does not place output pins in Hi-Z. 5. This instruction is reserved for future use.
0
0
0
0
0 0
6111 drw 17
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Scan Register Definition
Part 512Kx36 1Mx18 2Mx8/x9 Instrustion Register 3 bits 3 bits 3 bits Bypass Register 1 bit 1 bit 1 bit ID Register 32 bits 32 bits 32 bits Boundry Scan 107 bits 107 bits 107 bits
6111 tbl 14
Identification Register Definitions
INSTRUCTION FIELD Revision Number (31:29) Device ID (28:12) ALL DEVICES 000 0 0000 0010 0100 0000 0 0000 0010 0100 0001 0 0000 0010 0100 0010 0 0000 0010 0100 0011 000 0011 0011 1 DESCRIPTION Revision Number 512Kx36 1Mx18 2Mx9 2Mx8 QDRII BURST OF 4 71P74604S 71P74804S 71P74104S 71P74204S PART NUMBER
IDT JEDEC ID CODE (11:1) ID Register Presence Indicator (0)
Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
6111 tbl 15
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Boundary Scan Exit Order (2M x 8-Bit, 2M x 9-Bit)
ORDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PIN ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E
6111 tbl 16a
ORDER 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C
ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
PIN ID 3E 2C 1D 2E 1E 2F 3F 2G 3G 1F 1G 1J 2J 3K 3J 3L 2L 1K 2K 1M 1L 3N 3M 2N 3P 2M 1N 2P 1P 3R 4R 4P 5P 5N 5R
6111 tbl 18a
4B
99
3A
100
2A
101
1A 2B 3B 1C 1B 3D 3C 2D
6111 tbl 17a
102 103 104 105 106 107
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Boundary Scan Exit Order (1M x 18-Bit, 512K x 36-Bit)
ORDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PIN ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E
6111 tbl 16
ORDER 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D
6111 tbl 17
ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107
PIN ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
6111 tbl 18
6.42 18
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
JTAG DC Operating Conditions
P aram e te r O utp ut P o w e r S up p ly P o w e r S up p ly Vo ltag e Inp ut H ig h Le v e l Inp ut Lo w Le v e l O utp ut H ig h Vo ltag e (IO H = -1m A ) O utp ut Lo w Vo ltag e (IO L = 1m A ) Symbol V DD Q V DD V IH V IL V OH V OL M in 1.4 1.7 1.3 -0.3 V DD Q - 0.2 V SS Ty p 1.8 M ax 1.9 1.9 V DD + 0.3 0.5 V DD Q 0.2 U nit V V V V V V
1 1
6111 t b l 1 9
N o te
NOTE: 1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.
JTAG AC Test Conditions
Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level Symbol VIH/VIL TR/TF Min 1.3/0.5 1.0/1.0 VDDQ/2 Unit V ns V 1
6111 tbl 20
Note
NOTE: 1. See AC test load on page 12.
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min 50 20 20 5 5 5 5 5 5 0 Max 10 Unit ns ns ns ns ns ns ns ns ns ns
6111 tbl.21
Note
JTAG Timing Diagram
TC K
tC H C H tMVCH
tC H C L tC H M X
tC L C H
TMS
tD V C H
tC H D X
TD I/ SRAM Inp uts SRAM O utp uts
tC L Q V
tS V C H
tC H S X
TD O
6 1 1 1 d rw 1 9
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
6.42 20
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Ordering Information
IDT
71P74XXX Device Type
S Power
XXX Speed
BQ Package
X Process Temperature Range
Blank
Commercial (0 C to +70 C)
BQ 333 300 250 200 167
165 Fine Pitch Ball Grid Array (fBGA)
Clock Frequency in MegaHertz
IDT71P74204 IDT71P74104 IDT71P74804 IDT71P74604
2M x 8 QDR II SRAM Burst of 4 2M x 9 QDR II SRAM Burst of 4 1M x 18 QDR II SRAM Burst of 4 512K x 36 QDR II SRAM Burst of 4
6111 drw 15
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: sramhelp@idt.com 800-544-7726
"QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. "
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18 x -Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Revision History
REVISION O DATE 03/30/04 PAGES 1-21 DESCRIPTION Initial Advance Information Data Sheet Release

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